Portable electronic devices are ubiquitous accoutrements in modern life. Cellular telephones, smartphones, satellite navigation receivers, e-book readers and tablet computers, wearable computers (e.g., glasses, wrist computing), cameras, and music players are just a few examples of the many types of portable electronic devices in widespread use. Portable electronic devices are powered by batteries—either replaceable batteries such as alkaline cells, or rechargeable batteries such as NiCd, NiMH, LiOn, or the like. In either case, the useful life of portable electronic devices is limited by available battery power, which decreases in proportion to the length of use of the device, and the level of power consumption during that use.
Trends in portable electronic device design include higher levels of circuit integration, shrinking device form factors (and hence smaller batteries), increasing functionality, and wireless connectivity—all of which have made power management a critical area of optimization for portable electronic device designers.
Power management is particularly critical for very highly integrated circuits. Processing circuits, associated logic circuits (DMA, graphics processing, encryption, RF baseband processing, etc.) and memory are often integrated into the same IC die (or separate dice that are packaged together). This is known in the art as “System On a Chip,” or SOC. One approach to intelligent power management on SOC, which may include circuits having different power consumption profiles and operating frequencies, is to dynamically vary the clock frequency and voltage levels of power supplies during operation, in response to instantaneous demand (processing load, communications activity, and the like). This is known as Dynamic Voltage and Frequency Scaling (DVFS) or Dynamic Voltage Scaling (DVS). DVFS/DVS is routinely employed for battery-powered SOC, because maintaining voltage levels at the levels required for maximum operational performance will cause average battery power life to be significantly lower than when voltage levels are scaled dynamically along with the required performance. For example, for digital devices, supplying a voltage level 10% higher than required results in at least 21% higher power consumption drawn from the battery. DVFS/DVS is also advantageous from the perspective of thermal management.
SOC typically have a power architecture with numerous power rails running inside the silicon die (with different requirements for voltage, current, and power sequence). The power rails in the SOC are typically supplied from analog mixed signal components, such as voltage regulators (also called as power supplies). The voltage regulator outputs typically have a built-in slew rate control, to protect the system from battery surge currents when the regulator output voltages are changed.
There are usually some dependencies between power rails in the SOC due to the fact that two or more power supplies are fed to single components at many places of the die. For example, this is the case for level shifter components that are inserted when signals traverse from one power domain to another. The level shifter is then connected to the supplies of both power domains. However, in some situations there are speed constraints that preclude the use of a traditional level shifter. One such case, where special constraint between the power supplies can exist on a SOC, is the on-chip memory. The supply voltage for the memory array (called Vmemory) is ideally higher than the supply voltage for the digital interface (called Vlogic). This is because the noise instability is higher for memory cell than for logic cells, and this is generally true for any kind of CMOS process designs. However, inserting level shifters between the memory array and its interface logic may not be practical, due to the number of such connections, and/or performance constraints. Accordingly, the two circuits may be operated at different voltages. However, the memory array voltage supply must meet certain voltage boundary conditions in order for the memory to work at the required speed.
For example, the voltage boundary conditions may be specified as:Vmemory−Vlogic<350 mV,andVlogic−Vmemory<200 mV.If one of the Vmemory or Vlogic supply voltages is changed, then the other must change accordingly to ensure that the voltage boundary conditions are met at all times, in order to guarantee proper memory operation. Since DVFS/DVS is required for reasonable power consumption for SOC, changing two power supplies in a precise, rapid and linked way is necessary for the SOC device to work correctly, and power efficiently.
One known SOC is a baseband processor for a wireless communication device. This chip includes both digital logic and on-chip memory, with the power supplies for both circuits tied together; a single voltage regulator supplies power for the entire chip. Because the memory array and digital logic voltages are tied together, the memory array cannot be operated at a higher voltage than the digital core logic. The allowed voltage range for digital core logic of the SOC is thus more narrow than otherwise possible, and hence the power consumption is higher than optimum.
Another known SOC—a more sophisticated solution for a wireless communication device—is a two-chip solution tightly integrating a baseband processor and RF transceiver. In this SOC, the memory array power supply is a Low Drop Out (LDO) regulator, and the digital logic power supply is a switching DCDC power supply. In this case, Vmemory is fixed, and Vlogic may vary over an acceptable range without violating the voltage boundary conditions. While this solution improves performance, it still restricts Vlogic, which in some use cases must be higher than it could otherwise be, due to Vmemory being fixed.
The simple solution of making both Vmemory and Vlogic independently variable is problematic. First, there can be unspecified delays between the commands that control Vmemory and those that control Vlogic. This can result in the voltage boundary conditions to be broken temporarily. Second, the voltages may have different ramp times, making it complicated to adjust the delay between two commands. Third, since the voltage changes are driven by operating conditions, there can be a sudden need to achieve a new operation point while the transition to a previous one is still in progress, resulting voltage trajectories that are difficult to predict, and which hence may violate boundary conditions.
The changes to Vmemory and Vlogic could be broken into numerous small steps, and the incremental changes interleaved between the two voltage supplies. This would make it possible to adjust the voltages without violating boundary conditions. However, it would introduce significant delay, resulting in increased power consumption. In some cases, such an approach may fail to achieve required supply levels quickly enough to meet operational demands.
The Background section of this document is provided to place embodiments of the present invention in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.